Datasheet

VIO
PERIPH1
Device
VIO
PERIPH2
VIO
PERIPHn
CLKREQ
032-064
TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the
CLKREQ pin. As a result, the TPS65950 immediately sets CLKEN to 1 to warn the clock provider in the
system about the clock request and starts a timer (maximum of 5.2 ms using the 32.768-kHz clock). When
the timer expires, the TPS65950 opens a gated clock, the timer automatically reloads the defined value,
and a high-frequency output clock signal is available through the HFCLKOUT pin. The output drive of
HFCLKOUT is programmable (minimum load 10 pF, maximum load 40 pF) and must be at 40 pF by
default.
With a register setting, the mirroring of CLKEN can be enabled on CLKEN2. When this mirroring feature is
not enabled, CLKEN2 can be used as a GP output controlled through I
2
C accesses.
CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.
Figure 12-3 shows an example of the wired-OR clock request.
Figure 12-3. Example of Wired-OR Clock Request
134 Clock Specifications Copyright © 2008–2011, Texas Instruments Incorporated
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