Datasheet

TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
9 MADC
9.1 General Description
The TPS65950 shares the MADC resource with the host processors in the system (hardware and
software conversion modes) and its BCI. Therefore, the TPS65950 must:
• Manage potential concurrent requests of conversions and priority among resource users
• Flag, using interrupt signals, the end-of-sequence of conversions
• Grant quarter-bit accuracy for modem conversion of battery voltage
The quarter-bit accurate start signal is provided through a STARTADC from the host processor (real-time
conversion).
The MADC generates interrupt signals to the host processors. Interrupts are handled primarily by the
MADC internal secondary interrupt handler (SIH) and secondly at the upper level (outside the MADC) by
the TPS65950 primary interrupt handler (PIH). The MADC indicates to the BCI module, through a data
ready signal, that conversion results are available.
9.2 Main Electrical Characteristics
Table 9-1 lists the electrical characteristics of the MADC.
Table 9-1. Electrical Characteristics
Parameter Conditions Min Typ Max Unit
Resolution 10 Bit
Input dynamic range for external input Except ADIN0 and ADCIN1 and internal MADC 0 2.5 V
input (0 to 1.5 V)
MADC voltage reference 1.5 V
Differential nonlinearity For all channels (except ADIN2 through ADIN7 –1 1 LSB
channels)
Integral nonlinearity Best fitting. For all channels (except ADIN2 –2 2 LSB
through ADIN7)
Differential nonlinearity for ADIN2 through –1 1 LSB
ADIN7
Best fitting for codes 230 to maximum –2 2 LSB
Integral nonlinearity for ADIN2 through
Best fitting considering offset of 25 –3.75 3.75 LSB
ADIN7
least-significant bits (LSBs)
Offset Best fitting –28.5 28.5 mV
Input bias 1 μA
Input capacitor C
BANK
10 pF
Maximum source input resistance Rs (for 100 kΩ
all 16 internal or external inputs)
Input current leakage (for all 16 internal or 1 μA
external inputs)
126 MADC Copyright © 2008–2011, Texas Instruments Incorporated
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