Datasheet

TPS65950
SWCS032E–OCTOBER 2008–REVISED JANUARY 2011 www.ti.com
7.2.4 PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers required for
physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through UTMI.
There are two main classes of transmitters and receivers in the PHY:
• FS and LS transceivers. These are the legacy USB1.x transceivers.
• HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
• A digital phase-locked loop (DPLL) that does a frequency multiplication to achieve the 480-MHz
low-jitter lock necessary for USB, and the clock required for the switched capacitor resistance block
• A switched capacitor resistance block that replicates an external resistor on chip
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
The PHY also contains circuitry that protects it from an accidental 5-V short on the DP and DM lines and
from 8-kV IEC ESD strikes.
7.2.4.1 5-V Tolerance
When the voltage on DP or DM exceeds 3.6 V, a stress condition is detected. In this case, the current is
drawn from the DP/DM line, to prevent damage caused by the stress voltage. In this condition, the
VRUSB_3V supply can be charged as high as 3.6 V. Table 7-6 lists the tolerances.
Table 7-6. 5V-Tolerant Electrical Summary
Parameter Comments Min Typ Max Unit
Continuous short-circuit 50% TX/50% RX/50% LS/50% FS/VBUS = 5.25
DCSTRESS 24 h
stress V
t
HI
= 60 ns/t
LO
= 100 ns/t
R
= t
F
= 4 ns/
Worst case overshoot and
ACSTRESS V
HI
= 4.6 V/VLO = –1.0 V/R
SRC
= 39Ω/ 24 h
undershoot stress
50% TX/50% RX/VBUS = 5.25 V
Internal DP/DM stress
VDX_STRESS Force 5.25 V VBUS/DP/DM 4.3 V
voltage
V3P1_STRES
V3P1 stress voltage Force 5.25 V VBUS/DP/DM/ID 3.6 V
S
DP/DM input stress current IDX_STRESS Force 5.25 V VBUS/DP/DM 30 mA
ID input stress current IID_STRESS Force 5.25 V VBUS/DP/DM/ID 25 μA
7.2.4.2 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the
FS/LS modes of operation. Table 7-7 lists the parameters of the LS/FS single-ended receivers.
Table 7-7. LS/FS Single-Ended Receivers
Parameter Comments Min Typ Max Unit
USB Single-Ended Receivers
Skew between VP and VM SKWVP_VM Driver outputs unloaded –2 0 2 ns
Single-ended hysteresis V
SE_HYS
0 mV
High (driven) V
IH
2 V
Low V
IL
0.8 V
Switching threshold V
TH
0.8 2 V
106 USB HS 2.0 OTG Transceiver Copyright © 2008–2011, Texas Instruments Incorporated
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