Datasheet

UCLK
STP
DIR_&_NXT
DATA[7:0]
Data_OUT Data_IN
HSU0
HSU3
HSU3
HSU6 HSU7
HSU1 HSU1
HSU4
HSU5
HSU2 HSU2
032-054
TPS65950
www.ti.com SWCS032E–OCTOBER 2008–REVISED JANUARY 2011
7.2.3 HS USB Port Timing
The ULPI interface supports an 8-bit data bus and the internal clock mode. The 4-bit data bus and the
external clock mode are not supported.
The HS functional mode supports an operating rate of 480 Mbps.
Table 7-4 and Table 7-5 assume testing over the recommended operating conditions (see Figure 7-7).
Figure 7-7. HS USB Interface—Transmit and Receive Modes (ULPI 8-Bit)
NOTE
ULPI data [7:0] lines are set to 1 after USB PHY power up, and before the clock signal is
stable.
The input timing requirements are given by considering a rising or falling time of 1 ns.
Table 7-4. HS USB Interface Timing Requirement Parameters
Notation Parameter Min Max Unit
HSU4 t
s(STPV-CLKH)
Setup time, STP valid before UCLK rising edge 6 ns
HSU5 t
h(CLKH-STPIV)
Hold time, STP valid after UCLK rising edge 0 ns
HSU6 t
s(DATAV-CLKH)
Setup time, DATA[0:7] valid before UCLK rising edge 6 ns
HSU7 t
h(CLKH-DATIV)
Hold time, DATA[0:7] valid after UCLK rising edge 0 ns
Table 7-5. HS USB Interface Switching Requirement Parameters
(1)
Notation Parameter Min Typ Max Unit
HSU0 f
p(CLK)
UCLK clock frequency Steady state 58.42 60 61.67 MHz
HSU1 t
W(CLK)
UCLK duty cycle Steady state 48.3% 50% 51.7%
Delay time, UCLK rising edge to DIR Steady state 0 9
t
d(CLKH-DIR)
ns
transition
HSU2
Delay time, UCLK rising edge to NXT Steady state 0 9
t
d(CLKH-NXTV)
ns
transition
Delay time, UCLK rising edge to DATA[0:7] Steady state 0 9
HSU3 t
d(CLKH-DATV)
ns
transition
(1) The capacitive load for output data and control load is 10 pF (rising and falling time is 2 ns).
The capacitive load for the CLK port is 6 pF (rising and falling time is 1 ns).
The HS USB interface has only one state: steady state.
Copyright © 2008–2011, Texas Instruments Incorporated USB HS 2.0 OTG Transceiver 105
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