Datasheet

TPS65930/TPS65920
www.ti.com SWCS037G–MAY 2008–REVISED APRIL 2011
The input timing requirements in Table 12-5 are given by considering a rising or falling time of 6.5 ns.
Table 12-5. I2S Interface—Timing Requirements
Notation Parameter Min Max Unit
Master Mode
I3 t
su(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high2 25 ns
I4 t
h(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high. 0 ns
Slave Mode
I0 t
c(CLK)
Cycle time, I2S.CLK
(1)
1/64 * Fs ns
I1 t
w(CLK)
Pulse duration, I2S.CLK high or low
(2)
0.45 * P 0.55 * P ns
I3 t
su(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high 5 ns
I4 t
h(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high. 5 ns
I6 t
su(SYNC-CLKH)
Setup time, I2S.SYNC valid to I2S.CLK high 5 ns
I7 t
h(SYNC-CLKH)
Hold time, I2S.SYNC valid from I2S.CLK high 5 ns
(1) Fs = 8 to 48 kHz; 96 kHz for RX path only
(2) P = I2S.CLK period
The capacitive load for Table 12-6 is 7 pF. Table 12-6 lists the switching characteristics for the I2S
interface.
Table 12-6. I2S Interface—Switching Characteristics
Notation Parameter Min Max Unit
Master Mode
I0 t
c(CLK)
Cycle time, I2S.CLK
(1)
1/64 * Fs ns
I1 t
w(CLK)
Pulse duration, I2S.CLK high or low
(2)
0.45 * P 0.55 * P ns
I2 t
d(CLKL-SYNC)
Delay time, I2S.CLK falling edge to I2S.SYNC –10 10 ns
transition
I5 t
d(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT –10 10 ns
transition
Slave Mode
I5 t
d(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT 0 20 ns
transition
(1) Fs = 8 to 48 kHz; 96 kHz for RX path only
(2) P = I2S.CLK period
Copyright © 2008–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 99
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