Datasheet

I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0
8dummybits
23
22 1
0
8dummybits
23
22
23
22 1
0
8dummybits
23
22
1
0
8dummybits
23
22
Leftchannel
Rightchannel
I2 I2 I2
I3 I3 I3
I3
I4 I4
I4
I4
I5
I5
I5 I5
I0 I1
I1
037-031
I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23
22 1
0
8dummybits
23
22
1
0
8dummybits
23
22
23
22 1
0
8dummybits
23
22 1
0
8dummybits
23
22
Leftchannel Rightchannel
I3 I3 I3 I3
I4 I4 I4 I4
I5 I5 I5 I5
I6 I7 I6I0 I1
I1
037-032
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011 www.ti.com
12.4.1 I2S Right- and Left-Justified Data Format
Table 12-5 and Table 12-6 assume testing over the recommended operating conditions (see Figure 12-2
and Figure 12-3).
Figure 12-2. I2S Interface—I2S Master ModeI
Figure 12-3. I2S Interface—I2S Slave Mode
The timing requirements listed in Table 12-5 are valid on the following conditions of input slew and output
load:
• Rise and fall time range of inputs (SYNC, DIN) is t
R
/t
F
= 1.0 ns/6.5 ns
• Capacitance load range of outputs (CLK, SYNC, DOUT) is C
Load
= 1 pF/30 pF
98 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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