Datasheet

TPS65930/TPS65920
www.ti.com SWCS037G–MAY 2008–REVISED APRIL 2011
Table 12-4. I
2
C Interface—Switching Requirements
(1) (2)
Notation Parameter Min Max Unit
Slave HS Mode
I1 t
w(SCLL)
Pulse duration, SCL low 160 ns
I2 t
w(SCLH)
Pulse duration, SCL high 60 ns
Slave Fast-Speed Mode
I1 t
w(SCLL)
Pulse duration, SCL low 1.3
(3)
µs
I2 t
w(SCLH)
Pulse duration, SCL high 0.6 µs
Slave Standard Mode
I1 t
w(SCLL)
Pulse duration, SCL low 4.7 µs
I2 t
w(SCLH)
Pulse duration, SCL high 4 µs
(1) The capacitive load is:
100 pF in HS mode (3.4 Mbps)
400 pF in fast-speed mode (400 Kbps)
400 pF in standard mode (100 Kbps)
(2) SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
(3) SCL low timing for slave fast-speed mode is compatibile with 0.79 µs.
12.4 Audio Interface: TDM/I2S Protocol
The TPS65920/TPS65930 device acts as a master for the TDM and I2S interfaces or as a slave for only
the I2S interface. If the TPS65920/TPS65930 device is the master, it must provide the frame
synchronization (TDM/I2S_SYNC) and bit clock (TDM/I2S_CLK) to the host processor. If it is the slave,
the TPS65920/TPS65930 device receives frame synchronization and the bit clock.
The TPS65920/TPS65930 device supports the I2S, TDM, left-justified, and right-justified data formats, but
does not support TDM slave mode.
Copyright © 2008–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 97
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