Datasheet
I2C.SCL
I2C.SDA
1 8 9 1 8 9
MSB LSB
ACK
MSB LSB
ACK
I1 I2
I3 I4
I7
I8
I8
I9
START RESTART STOP
037-033
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
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12.3 I
2
C Timing
The TPS65920/TPS65930 device provides two I
2
C HS slave interfaces (one for general-purpose and one
for SmartReflex). These interfaces support standard mode (100 Kbps), fast mode (400 Kbps), and HS
mode (3.4 Mbps). The general-purpose I
2
C module embeds four slave hard-coded addresses (ID1 = 48h,
ID2 = 49h, ID3 = 4Ah, and ID4 = 4Bh). The SmartReflex I
2
C module uses one slave hard-coded address
(ID5). The master mode is not supported.
Table 12-3 and Table 12-4 assume testing over the recommended operating conditions (see Figure 12-1).
Figure 12-1. I
2
C Interface—Transmit and Receive in Slave Mode
Table 12-3. I
2
C Interface—Timing Requirements
(1) (2)
Notation Parameter Min Max Unit
Slave HS Mode
I3 t
su(SDA-SCLH)
Setup time, SDA valid to SCL high 10 ns
I4 t
h(SCLL-SDA)
Hold time, SDA valid from SCL low 0 70 ns
I7 t
su(SCLH-SDAL)
Setup time, SCL high to SDA low 160 ns
I8 t
h(SDAL-SCLL)
Hold time, SCL low from SDA low 160 ns
I9 t
su(SDAH-SCLH)
Setup time, SDA high to SCL high 160 ns
Slave Fast-Speed Mode
I3 t
su(SDA-SCLH)
Setup time, SDA valid to SCL high 100 ns
I4 t
h(SCLL-SDA)
Hold time, SDA valid from SCL low 0 0.9 ns
I7 t
su(SCLH-SDAL)
Setup time, SCL high to SDA low 0.6 ns
I8 t
h(SDAL-SCLL)
Hold time, SCL low from SDA low 0.6 ns
I9 t
su(SDAH-SCLH)
Setup time, SDA high to SCL high 0.6 ns
Slave Standard Mode
I3 t
su(SDA-SCLH)
Setup time, SDA valid to SCL high 250 ns
I4 t
h(SCLL-SDA)
Hold time, SDA valid from SCL low 0 ns
I7 t
su(SCLH-SDAL)
Setup time, SCL high to SDA low 4.7 ns
I8 t
h(SDAL-SCLL)
Hold time, SCL low from SDA low 4 ns
I9 t
su(SDAH-SCLH)
Setup time, SDA high to SCL high 4 ns
(1) The input timing requirements are given by considering a rising or falling time of:
80 ns in HS mode (3.4 Mbps)
300 ns in fast-speed mode (400 Kbps)
1000 ns in standard mode (100 Kbps)
(2) SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA.
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL.
Table 12-4 lists the switching requirements of the I
2
C interface.
96 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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