Datasheet

VBAT
DEVOFF(register)
NRESPWRON
REGEN
32K OUTCLK
DCDCs
LDOs
SYSEN
HFCLKOUT
CLKEN
NEXT_Startup_event
18 sm
1.2ms
1.2ms
1.2ms
18 sm
18 sm
18 sm
3.42msbeforedetectionofstartingevent
126 sm
037-055
TPS65930/TPS65920
www.ti.com SWCS037G–MAY 2008–REVISED APRIL 2011
4.5.4 Power-Off Sequence
This section describes the signal behavior required to power down the system.
4.5.4.1 Power-Off Sequence
Figure 4-11 shows the timing and control that occur during the power-off sequence in master modes.
NOTE: All of these timings are typical values with the default setup (depending on the resynchronization between power
domains, state machinery priority, etc.).
Figure 4-11. Power-Off Sequence in Master Modes
Because of the internal frequency used by Power STM switching from 3 to 1.5 MHz when the HF clock
value is 19.2 MHz, if the HF clock value is not 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly in the CFG_BOOT register), the delay between DEVOFF and
NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by two (approximately 9 μs).
The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master
mode.
Copyright © 2008–2011, Texas Instruments Incorporated Power Module 53
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