Datasheet

Sequence_Start
REGEN
VIO
VPLL1
VDD2
VDD1
32K OUTCLK
SYSEN
CLKEN
HFCLKOUT
NRESPWRON
4608 msbatterydetection
1068 ms-3MHzoscillatorsetting+clockswitch
1099 msforVDD2stabilizationandVDD1startramping
1179 msforVIOstabilization
1022 msforLDOstabilizationandstartdc-dcramping
61 ms
~5.3ms
61 ms
1953 ms
1175 msforVDD1stabilization
1179 msforVIOstabilization
1.8V
1.8V
1.2V
1.2V
019-072
TPS65930/TPS65920
www.ti.com SWCS037G–MAY 2008–REVISED APRIL 2011
4.5.3.2 Power-On Sequence
Figure 4-9 describes the timing and control that must occur in the OMAP3 mode. Sequence_Start is a
symbolic internal signal to ease the description of the power sequences. It occurs according to the events
shown in Figure 4-8.
Figure 4-9. Timings–Power On in OMAP3 Mode
4.5.3.3 Power On in Slave_C021 Mode
Figure 4-10 describes the timing and control that must occur in the Slave_C021 mode. Sequence_Start is
a symbolic internal signal to ease the description of the power sequences and occurs according to the
different events detailed in Figure 4-8
Copyright © 2008–2011, Texas Instruments Incorporated Power Module 51
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