Datasheet

TPS65930/TPS65920
www.ti.com SWCS037G–MAY 2008–REVISED APRIL 2011
4.1.5 VPLL1 LDO Regulator
The VPLL1 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host
processor PLL supply. Table 4-7 describes the regulator characteristics.
Table 4-7. VPLL1 LDO Regulator Characteristics
Parameter Test Conditions Min Typ Max Unit
Output Load Conditions
Filtering capacitor Connected from VPLL1.OUT to analog ground 0.3 1 2.7 μF
Filtering capacitor ESR 20 600 mΩ
Electrical Characteristics
V
IN
Input voltage 2.7 3.6 4.5 V
V
OUT
Output voltage On mode and low-power mode 0.97 1.0 1.03 V
1.164 1.2 1.236
1.261 1.3 1.339
1.746 1.8 1.854
2.716 2.8 2.884
2.91 3.0 3.090
I
OUT
Rated output current On mode 40 mA
Low-power mode 5
dc load regulation On mode: 0 < I
O
< I
Max
20 mV
dc line regulation On mode, V
IN
= V
INmin
to V
INmax
at I
OUT
= I
OUTmax
3 mV
Turn-on time I
OUT
= 0, C
L
= 1 μF (within 10% of V
OUT
) 100 μs
Wake-up time Full load capability 10 μs
Ripple rejection f < 10 kHz 50 dB
10 kHz < f < 100 kHz 40
f = 1 MHz 30
V
IN
= V
OUT
+ 1 V, I
O
= I
Max
Ground current On mode, I
OUT
= 0 70 μA
On mode, I
OUT
= I
OUTmax
110
Low-power mode, I
OUT
= 0 15
Low-power mode, I
OUT
= 1 mA 16
Off mode at 55°C 1
V
DO
Dropout voltage On mode, I
OUT
= I
OUTmax
250 mV
I
Load
: I
Min
– I
Max
Transient load regulation –40 40 mV
Slew: 60 mA/μs
V
IN
drops 500 mV
Transient line regulation 10 mV
Slew: 40 mV/μs
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