Datasheet

TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011 www.ti.com
4.1.4 VDAC LDO Regulator
The VDAC programmable LDO regulator is a high-PSRR, low-noise linear regulator that powers the host
processor dual-video DAC. It is controllable with registers through I
2
C and can be powered down.
Table 4-6 describes the regulator characteristics.
Table 4-6. VDAC LDO Regulator Characteristics
Parameter Test Conditions Min Typ Max Unit
Output Load Conditions
Filtering capacitor Connected from VDAC.OUT to analog ground 0.3 1 2.7 μF
Filtering capacitor ESR 20 600 mΩ
Electrical Characteristics
V
IN
Input voltage 2.7 3.6 4.5 V
V
OUT
Output voltage On mode 1.164 1.2 1.236 V
1.261 1.3 1.339
1.746 1.8 1.854
I
OUT
Rated output current On mode 70 mA
Low-power mode 5
dc load regulation On mode: 0 < I
O
< I
Max
20 mV
dc line regulation On mode, V
IN
= V
INmin
to V
INmax
at I
OUT
= I
OUTmax
3 mV
Turn-on time I
OUT
= 0, C
L
= 1 μF (within 10% of V
OUT
) 100 μs
Wake-up time Full load capability 10 μs
Ripple rejection f < 20 kHz 65 dB
20 kHz < f < 100 kHz 45
f = 1 MHz 40
V
IN
= V
OUT
+ 1 V, I
O
= I
Max
Output noise 100 Hz < f < 5 kHz 400 nV/√Hz
5 kHz < f < 400 kHz 125
400 kHz < f < 10 MHz 50
Ground current On mode, I
OUT
= 0 150 μA
On mode, I
OUT
= I
OUTmax
350
Low-power mode, I
OUT
= 0 15
Low-power mode, I
OUT
= 1 mA 25
Off mode at 55°C 1
V
DO
Dropout voltage On mode, I
OUT
= I
OUTmax
250 mV
I
Load
: I
Min
– I
Max
Transient load regulation –40 40 mV
Slew: 60 mA/μs
V
IN
drops 500 mV
Transient line regulation 10 mV
Slew: 40 mV/μs
38 Power Module Copyright © 2008–2011, Texas Instruments Incorporated
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