Datasheet

JTAG.TCK
JTAG.TDI
JTAG.TMS
JTAG.TDO
JL1
JL2 JL2
JL7
JL3 JL4
JL6JL5
jtag_inter_time_wcs019
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011 www.ti.com
Figure 12-5. JTAG Interface Timing
The input timing requirements are given by considering a rising or falling edge of 7 ns.
Table 12-9. JTAG Interface—Timing Requirements
Notation Parameter Min Max Unit
Clock
JL1 t
c(TCK)
Cycle time, JTAG.TCK period 30 ns
JL2 t
w(TCK)
Pulse duration, JTAG.TCK high or low
(1)
0.48*P 0.52*P ns
Read Timing
Setup time, JTAG.TDI valid before JTAG.TCK
JL3 t
su(TDIV-TCKH)
8 ns
high
JL4 t
h(TDIV-TCKH)
Hold time, JTAG.TDI valid after JTAG.TCK high 5 ns
Setup time, JTAG.TMS valid before JTAG.TCK
JL5 t
su(TMSV-TCKH)
8 ns
high
JL6 t
h(TMSV-TCKH)
Hold time, JTAG.TMS valid after JTAG.TCK high 5 ns
(1) P = JTAG.TCK clock period
The capacitive load is 35 pF.
Table 12-10. JTAG Interface—Switching Characteristics
Notation Parameter Min Max Unit
Write Timing
JL7 t
d(TCK-TDOV))
Delay time, JTAG, TCK active edge to JTAG.TDO valid 0 14 ns
102 Timing Requirements and Switching Characteristics Copyright © 2008–2011, Texas Instruments Incorporated
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