Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Bits Field Name Description Type Reset
1 GPIO0_F_IT_MSK GPIO0 falling-edge detection interrupt mask. RW 1
0 GPIO0_R_IT _MSK GPIO0 rising-edge detection interrupt mask. RW 1
Table 79. INT_STS3_REG
Address Offset 0x54
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
PWRDN_IT VMBCH2_L_IT VMBCH2_H_IT WTCHDG_IT GPIO5_F_IT GPIO5_R_IT GPIO4_F_IT GPIO4_R_IT
Bits Field Name Description Type Reset
7 PWRDN_IT PWRDN reset input high detected RW 0
W1 to Clr
6 VMBCH2_L_IT Comparator2 input below threshold detection interrupt status RW 0
W1 to Clr
5 VMBCH2_H_IT Comparator2 input above threshold detection interrupt status RW 0
W1 to Clr
4 WTCHDG_IT Watchdog interrupt status RW 0
W1 to Clr
3 GPIO5_F_IT GPIO5 falling-edge detection interrupt status RW 0
W1 to Clr
2 GPIO5_R_IT GPIO5 rising-edge detection interrupt status RW 0
W1 to Clr
1 GPIO4_F_IT GPIO4 falling-edge detection interrupt status RW 0
W1 to Clr
0 GPIO4_R_IT GPIO4 rising-edge detection interrupt status RW 0
W1 to Clr
Table 80. INT_MSK3_REG
Address Offset 0x55
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type RW
7 6 5 4 3 2 1 0
PWRDN_IT_MSK
GPIO5_F_IT_MSK GPIO4_F_IT_MSK
GPIO5_R_IT_MSK GPIO4_R_IT_MSK
WTCHDG_IT_MSK
VMBCH2_L_IT_MSK
VMBCH2_H_IT_MSK
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