Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Bits Field Name Description Type Reset
4 PWRHOLD_R_IT Rising PWRHOLD event interrupt status. RW 0
W1 to Clr
3 PWRON_LP_IT PWRON Long Press event interrupt status. RW 0
W1 to Clr
2 PWRON_IT PWRON event interrupt status. RW 0
W1 to Clr
1 VMBHI_IT VBAT > VMHI event interrupt status RW 0
W1 to Clr
0 PWRHOLD_F_IT Falling PWRHOLD event interrupt status. RW 0
W1 to Clr
Table 76. INT_MSK_REG
Address Offset 0x51
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type RW
7 6 5 4 3 2 1 0
VMBHI_IT_MSK
HOTDIE_IT_MSK
PWRON_IT_MSK
PWRON_LP_IT_MSK
RTC_ALARM_IT_MSK
PWRHOLD_F_IT_MSK
PWRHOLD_R_IT_MSK
RTC_PERIOD_IT_MSK
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT_MS RTC period event interrupt mask. RW 1
K
6 RTC_ALARM_IT_MS RTC alarm event interrupt mask. RW 1
K
5 HOTDIE_IT_MSK Hot die event interrupt mask. RW 1
4 PWRHOLD_R_IT_MS PWRHOLD rising-edge event interrupt mask. RW 1
K
3 PWRON_LP_IT_MSK PWRON Long Press event interrupt mask. RW 1
2 PWRON_IT_MSK PWRON event interrupt mask. RW 1
1 VMBHI_IT_MSK VBAT > VMBHI interrupt event mask bit RW 1
When 0, interrupt not masked. Device automatically switches on at NO
SUPPLY-to-OFF BACKUP-to-OFF transition
When 1, interrupt is masked. Device does not switch on until a start
reason is received.
(EEPROM bit. Default value: See boot configuration)
0 PWRHOLD_F_IT_MS PWRHOLD falling-edge event interrupt mask. RW 1
K
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