Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Bits Field Name Description Type Reset
3 VDDCTRL_EN2 When control bit = 1: RW 0
When EN2 is high the supply voltage is programmed though
VDDCtrl_OP_REG register, and it can also be programmed off..
When EN2 is low the supply voltage is programmed though
VDDCtrl_SR_REG register, and it can also be programmed off.
When EN2 is low and and VDDCtrl_KEEPON = 1 the SMPS is working
in low-power mode, if not tuned off though VDDCtrl_SR_REG register.
When control bit = 0 no effect: Supply state is driven though registers
programming and the device state
2 VDD2_EN2 When control bit = 1: RW 0
When SDASR_EN2 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and SLEEP_KEEP_RES_ON = 1 the
SMPS is working in low-power mode, if not tuned off though
VDD2_SR_REG register.
When control bit = 0 no effect: Supply state is driven though registers
programming and the device state
1 VDD1_EN2 When control bit = 1: RW 0
When SDASR_EN2 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and SLEEP_KEEP_RES_ON = 1 the
SMPS is working in low-power mode, if not tuned off though
VDD1_SR_REG register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
0 VIO_EN2 When control bit = 1, RW 0
supply state is driven by the SCLSR_EN2 control signal and is also
defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low-power mode if
its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 no effect: SMPS state is driven though registers
programming and the device state
Table 75. INT_STS_REG
Address Offset 0x50
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
HOTDIE_IT PWRON_LP_IT PWRON_IT VMBHI_IT
RTC_ALARM_IT
PWRHOLD_F_IT
PWRHOLD_R_IT
RTC_PERIOD_IT
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT RTC period event interrupt status. RW 0
W1 to Clr
6 RTC_ALARM_IT RTC alarm event interrupt status. RW 0
W1 to Clr
5 HOTDIE_IT Hot-die event interrupt status. RW 0
W1 to Clr
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