Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Table 73. EN2_LDO_ASS_REG (continued)
Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also
defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I
2
C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
LDO3_EN2 LDO4_EN2 LDO7_EN2 LDO8_EN2 LDO5_EN2 LDO2_EN2 LDO1_EN2 LDO6_EN2
Bits Field Name Description Type Reset
7 LDO3_EN2 Setting supply state control though SDASR_EN2 signal RW 0
6 LDO4_EN2 Setting supply state control though SDASR_EN2 signal RW 0
5 LDO7_EN2 Setting supply state control though SDASR_EN2 signal RW 0
4 LDO8_EN2 Setting supply state control though SDASR_EN2 signal RW 0
3 LDO5_EN2 Setting supply state control though SDASR_EN2 signal RW 0
2 LDO2_EN2 Setting supply state control though SDASR_EN2 signal RW 0
1 LDO1_EN2 Setting supply state control though SDASR_EN2 signal RW 0
0 LDO6_EN2 Setting supply state control though SDASR_EN2 signal RW 0
Table 74. EN2_SMPS_ASS_REG
Address Offset 0x48
Physical Address Instance (RESET DOMAIN: TURNOFF
RESET)
Description Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I
2
C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
Reserved SPARE_EN2 VDD2_EN2 VDD1_EN2 VIO_EN2
VDDCTRL_EN2
Bits Field Name Description Type Reset
7:5 Reserved RO 0x0
R returns
0s
4 SPARE_EN2 Spare bit RW 0
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