Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Bits Field Name Description Type Reset
7 DEFAULT_VOLT When 1, default voltages (register value after switch-on) will be applied RW 0
to all resources during SLEEP-to-ACTIVE transition.
When 0, voltages programmed before the ACTIVE-to-SLEEP state
transition will be used to turned-on supplies during SLEEP-to-ACTIVE
state transition.
6:5 Reserved RO 0x0
R returns
0s
4 SPARE_SETOFF Spare bit RW 0
3 VDDCTRL_SETOFF When 1, SMPS is turned off during device SLEEP state. RW 0
When 0, No effect.
2 VDD2_SETOFF When 1, SMPS is turned off during device SLEEP state. RW 0
When 0, No effect.
1 VDD1_SETOFF When 1, SMPS is turned off during device SLEEP state. RW 0
When 0, No effect.
0 VIO_SETOFF When 1, SMPS is turned off during device SLEEP state. RW 0
When 0, No effect.
Table 71. EN1_LDO_ASS_REG
Address Offset 0x45
Physical Address Instance (RESET DOMAIN: TURNOFF
RESET)
Description Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined
though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I
2
C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
LDO3_EN1 LDO4_EN1 LDO7_EN1 LDO8_EN1 LDO5_EN1 LDO2_EN1 LDO1_EN1 LDO6_EN1
Bits Field Name Description Type Reset
7 LDO3_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
6 LDO4_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
5 LDO7_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
4 LDO8_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
3 LDO5_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
2 LDO2_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
1 LDO1_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
0 LDO6_EN1 Setting supply state control though SCLSR_EN1 signal RW 0
Table 72. EN1_SMPS_ASS_REG
Address Offset 0x46
Physical Address Instance (RESET DOMAIN: TURNOFF
RESET)
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