Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
7 6 5 4 3 2 1 0
RTC_PWDN CK32K_CTRL DEV_ON DEV_SLP DEV_OFF
DEV_OFF_RST
PWR_OFF_SEQ
SR_CTL_I2C_SEL
Bits Field Name Description Type Reset
7 PWR_OFF_SEQ When 1, power-off will be sequencial, reverse of power-on sequence RW 0
(first resource to power on will be the last to power off).
When 0, all resources disabled at the same time
6 RTC_PWDN When 1, disable the RTC digital domain (clock gating and reset of RTC RW 0
registers and logic).
This register bit is not reset in BACKUP state.
5 CK32K_CTRL Internal 32-kHz clock source control bit (EEPROM bit): RW 0
when 0, the internal 32-kHz clock source is the crystal oscillator or an
external 32-kHz clock in case the crystal oscillator is used in bypass
mode
when 1, the internal 32-kHz clock source is the RC oscillator.
4 SR_CTL_I2C_SEL Voltage scaling registers access control bit: RW 1
when 0: access to registers by voltage scaling I
2
C
when 1: access to registers by control I
2
C. The voltage scaling registers
are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG,
VDD2_SR_REG, VDDCtrl_OP_REG, and VDDCtrl_SR_REG.
3 DEV_OFF_RST Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state RW 0
transition (switch-off event) and activate reset of the digital core.
This bit is cleared in OFF state.
2 DEV_ON Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if RW 0
DEV_OFF = 0 and DEV_OFF_RST = 0).
EEPROM bit
(Default value:See boot configuration)
1 DEV_SLP Write 1 allows SLEEP device state (if DEV_OFF = 0 and RW 0
DEV_OFF_RST = 0).
Write ‘0’ will start an SLEEP-to-ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
0 DEV_OFF Write 1 will start an ACTIVE-to-OFF or SLEEP-to-OFF device state RW 0
transition (switch-off event). This bit is cleared in OFF state.
Table 66. DEVCTRL2_REG
Address Offset 0x40
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description Device control register TSLOT_LENGTH: TURN OFF
RESET
Type RW
7 6 5 4 3 2 1 0
Reserved TSLOT_LENGTH IT_POL
PWON_LP_OFF PWON_LP_RST
SLEEPSIG_POL
DCDC_SLEEP_LVL
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