Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Bits Field Name Description Type Reset
7:3 Reserved Reserved bit RO 0x00
R returns
0s
2:1 BBSEL Back up battery charge voltage selection: RW 0x0
BBSEL[1:0] = 00: 3.0 V
BBSEL[1:0] = 01: 2.52 V
BBSEL[1:0] = 10: 3.15 V
BBSEL[1:0] = 11: VBAT
0 BBCHEN Back up battery charge enable RW 0
Table 64. DCDCCTRL_REG
Address Offset 0x3E
Physical Address Instance RESET DOMAIN:
bits [7:3]: TURNOFF OFF RESET
bits [2:0]: GENERAL RESET
Description DCDC control register
Type RW
7 6 5 4 3 2 1 0
Reserved TRACK VDD2_PSKIP VDD1_PSKIP VIO_PSKIP DCDCCKEXT DCDCCKSYNC
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO 0
R returns
0s
6 TRACK 1: Tracking mode: LDO4 output follows VDD1 setting when VDD1 active. RW 0
See appendix for more information.
0: Normal LDO operation without tracking
5 VDD2_PSKIP VDD2 pulse skip mode enable (EEPROM bit) RW 1
Default value: See boot configuration
4 VDD1_PSKIP VDD1 pulse skip mode enable (EEPROM bit) RW 1
Default value: See boot configuration
3 VIO_PSKIP VIO pulse skip mode enable (EEPROM bit) RW 1
Default value: See boot configuration
2 DCDCCKEXT This signal control the muxing of the GPIO2 pad: RW 0
When 0: this pad is a GPIO
When 1: this pad is used as input for an external clock used for the
synchronisation of the DCDCs
1:0 DCDCCKSYNC DCDC clock configuration: RW 0x1
DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11: DCDC synchronous clock
Table 65. DEVCTRL_REG
Address Offset 0x3F
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description Device control register Bit 0,1, and 3 : TURN OFF RESET
Type RW
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