Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO 0x00
R returns
0s
1:0 ST Supply state (EEPROM dependent): RW 0x0
ST[1:0] = 00: Off
ST[1:0] = 01: On
ST[1:0] = 10: Off
ST[1:0] = 11: On
Table 52. VDDCRTL_OP_REG
Address Offset 0x28
Physical Address Instance (RESET DOMAIN: TURN OFF
RESET)
Description VDDCtrl voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I
2
C interfaces depending
on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
CMD SEL
Bits Field Name Description Type Reset
7 CMD Command: RW 0
when 0: VDDctrl_OP_REG voltage is applied
when 1: VDDctrl_SR_REG voltage is applied
6:0 SEL Output voltage (4 EEPROM bits) selection: RW 0x00
SEL[6:0] = 1000011 to 1111111: 1.4 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0010011: 0.8 V
...
SEL[6:0] = 0000001: 0000011 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 64 (dec)
Vout= (SEL[6:0] × 12.5 mV + 0.5625 V)
(Default value: See boot configuration)
Table 53. VDDCRTL_SR_REG
Address Offset 0x29
Physical Address Instance (RESET DOMAIN: TURN OFF
RESET)
Description VDDCtrl voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I
2
C interfaces depending
on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
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