Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Table 46. VDD1_OP_REG (continued)
Description VDD1 voltage selection register.
This register can be accessed by both control and coltage scaling I
2
C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
CMD SEL
Bits Field Name Description Type Reset
7 CMD when 0: VDD1_OP_REG voltage is applied RW 0
when 1: VDD1_SR_REG voltage is applied
6:0 SEL Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1, RW 0x00
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
Note: Vout maximum value is 3.3 V
Table 47. VDD1_SR_REG
Address Offset 0x23
Physical Address Instance (RESET DOMAIN: TURNOFF OFF
RESET)
Description VDD1 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I
2
C interfaces depending
on SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO 0
R returns
0s
6:0 SEL Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB): RW 0x00
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
Note: Vout maximum value is 3.3 V
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