Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L JUNE 2010REVISED MARCH 2014
www.ti.com
Bits Field Name Description Type Reset
7:6 ILMAX Select maximum load current: RW 0x0
when 00: 0.6 A
when 01: 1.0 A
when 10: 1.3 A
when 11: 1.3 A
5:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Output voltage selection (EEPROM bits): RW 0x0
SEL[1:0] = 00: 1.5 V
SEL[1:0] = 01: 1.8 V
SEL[1:0] = 10: 2.5 V
SEL[1:0] = 11: 3.3 V
(Default value: see boot configuration)
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
Table 45. VDD1_REG
Address Offset 0x21
Physical Address Instance (RESET DOMAIN: TURNOFF OFF
RESET)
Description VDD1 control register
Type RW
7 6 5 4 3 2 1 0
VGAIN_SEL ILMAX TSTEP ST
Bits Field Name Description Type Reset
7:6 VGAIN_SEL Select output voltage multiplication factor: G (EEPROM bits): RW 0x0
when 00: x1
when 01: x1
when 10: x2
when 11: x3
(Default value:see boot configuration)
5 ILMAX Select maximum load current: RW 0
when 0: 1.0 A
when 1: > 1.5 A
4:2 TSTEP Time step: when changing the output voltage, the new value is reached RW 0x3
through successive 12.5 mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 Mhz)
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 Mhz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 Mhz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 Mhz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 Mhz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 Mhz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 Mhz/5)
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00: Off
ST[1:0] = 01: On, high-power mode
ST[1:0] = 10: Off
ST[1:0] = 11: On, low-power mode
Table 46. VDD1_OP_REG
Address Offset 0x22
Physical Address Instance (RESET DOMAIN: TURNOFF OFF
RESET)
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