Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO 0x00
R returns
0s
1:0 ST Reference state: RO 0x1
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only)
Table 43. VRTC_REG
Address Offset 0x1E
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description VRTC internal regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved Reserved ST
VRTC_OFFMASK
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3 VRTC_OFFMASK VRTC internal regulator off mask signal: RW 0
when 1, the regulator keeps its full-load capability during device OFF
state.
when 0, the regulator will enter in low-power mode during device OFF
state.
Note that VRTC is put in low-power mode when the device is on backup
even if this bit is set to 1 (Default value: See boot configuration)
2 Reserved Reserved bit RO 0
R returns
0s
1:0 ST Reference state: RO 0x1
ST[1:0] = 00: Reserved
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only)
Table 44. VIO_REG
Address Offset 0x20
Physical Address Instance (RESET DOMAIN: TURNOFF OFF
RESET)
Description VIO control register
Type RW
7 6 5 4 3 2 1 0
ILMAX Reserved SEL ST
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