Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
7 6 5 4 3 2 1 0
RTC_COMP_MSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_MSB This register contains the number of 32-kHz periods to be added into the RW 0x00
32-kHz counter every hour [MSB]
Table 34. RTC_RES_PROG_REG
Address Offset 0x15
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register containing oscillator resistance value
Type RW
7 6 5 4 3 2 1 0
Reserved SW_RES_PROG
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO 0x0
R returns
0s
5:0 SW_RES_PROG Value of the oscillator resistance RW 0x27
Table 35. RTC_RESET_STATUS_REG
Address Offset 0x16
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for reset status
Type RW
7 6 5 4 3 2 1 0
Reserved
RESET_STATUS
Bits Field Name Description Type Reset
7:1 Reserved Reserved bit RO 0x0
R returns
0s
0 RESET_STATUS This bit can only be set to one and is cleared when a manual reset or a RW 0
POR (VBAT < 2.1)occur. If this bit is reset it means that the RTC has lost
its configuration.
Table 36. BCK1_REG
Address Offset 0x17
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
Type RW
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