Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
7 6 5 4 3 2 1 0
Reserved IT_ALARM IT_TIMER EVERY
IT_SLEEP_MASK_EN
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO 0x0
R returns
0s
4 IT_SLEEP_MASK_E 1: Mask periodic interrupt while the TPS65911 device is in SLEEP mode. RW 0
N Interrupt event is back up in a register and occurred as soon as the
TPS65911 device is no more in SLEEP mode.
0: Normal mode, no interrupt masked
3 IT_ALARM Enable one interrupt when the alarm value is reached (TC ALARM RW 0
registers) by the TC registers
2 IT_TIMER Enable periodic interrupt RW 0
0: interrupt disabled
1: interrupt enabled
1:0 EVERY Interrupt period RW 0x0
00: every second
01: every minute
10: every hour
11: every day
Table 32. RTC_COMP_LSB_REG
Address Offset 0x13
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32-kHz oscillator period every hour, micro-controller needs to write FFFF
into RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type RW
7 6 5 4 3 2 1 0
RTC_COMP_LSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_LSB This register contains the number of 32-kHz periods to be added into the RW 0x00
32-kHz counter every hour [LSB]
Table 33. RTC_COMP_MSB_REG
Address Offset 0x14
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type RW
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