Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO 0x0
R returns
0s
4 ALARM_MONTH1 Second digit of alarm programmation for months (range is 0 up to 1) RW 0
3:0 ALARM_MONTH0 First digit of alarm programmation for months (range is 0 up to 9) RW 0x1
Table 28. ALARM_YEARS_REG
Address Offset 0x0D
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC register for alarm programmation for years
Type RW
7 6 5 4 3 2 1 0
ALARM_YEAR1 ALARM_YEAR0
Bits Field Name Description Type Reset
7:4 ALARM_YEAR1 Second digit of alarm programmation for years (range is 0 up to 9) RW 0x0
3:0 ALARM_YEAR0 First digit of alarm programmation for years (range is 0 up to 9) RW 0x0
Table 29. RTC_CTRL_REG
Address Offset 0x10
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description RTC control register:
NOTES: A dummy read of this register is necessary before each I
2
C read in order to update the
ROUND_30S bit value.
Type RW
7 6 5 4 3 2 1 0
RTC_V_OPT GET_TIME TEST_MODE MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC
SET_32_COUNTER
Bits Field Name Description Type Reset
7 RTC_V_OPT RTC date/time register selection: RW 0
0: Read access directly to dynamic registers (SECONDS_REG,
MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,
YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit).
6 GET_TIME When writing a 1 into this register, the content of the dynamic registers RW 0
(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,
MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into
static shadowed registers. Each update of the shadowed registers needs
to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then
re-write it to 1)
5 SET_32_COUNTER 0: No action RW 0
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen.
4 TEST_MODE 0: functional mode RW 0
1: test mode (Auto compensation is enable when the 32-kHz counter
reaches at its end)
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