Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
9 Package Description
The following are the package descriptions of the TPS65911 PMU devices:
• Package type:
Package TPS65911
Type ZRC98 BGA Microstar Junior
Size (mm) 6x9
Substrate layers 1 layer
Pitch ball array (mm) 0.65 mm
Number of balls 98
Thickness (mm) (max. height including balls) 1
9.1 Package Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
(1)
TPS65911 UNITS
ZRC
98 pins
θJA Junction-to-ambient thermal 32 °C/W
resistance
(2)
θJC(TOP) Junction-to-case(top) thermal 18
resistance
(3)
θJB Junction-to-board thermal 16
resistance
(4)
ψJT Junction-to-top characterization 0.2
parameter
(5)
ψJB Junction-to-board 12
characterization parameter
(6)
θJC(BOTTOM) Junction-to-case(bottom) thermal N/A
resistance
(7)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
http://focus.ti.com/lit/an/spra953a/spra953a.pdf
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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