Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
NOTE
The compensation is considered once written into the registers.
8.8 Backup Battery Management
The device includes a back-up battery switch connecting the VRTC regulator input to a main battery (VCC7) or to
a back-up battery (VBACKUP), depending on the voltage value of the battery.
The VRTC supply can then be maintained during a BACKUP state as long as the input voltage is high enough (>
VBNPR threshold). Below the VBNPR voltage threshold, the digital core of the device is set under reset by
internal signal POR (PowerOnReset).
The back-up domain functions which are always supplied from VRTC are:
• The internal 32-kHz oscillator
• Back-up registers
The back-up battery can be charged from the main battery through an embedded charger. The back-up battery
charge voltage and enable is controlled through BBCH_REG register programming. This register content is
maintained during the device BACKUP state.
Hence, when enabled, the back-up battery charge is maintained as long as the main battery voltage is higher
than the VMBLO threshold and the back-up battery voltage.
8.9 Backup Registers
As part of the RTC, the device contains five 8-bit registers that can be used for storage by the application
firmware when the external host is powered down. These registers retain their content as long as the VRTC is
active.
8.10 I
2
C Interface
A general-purpose serial control interface (CTL-I
2
C) allows read and write access to the configuration registers of
all resources of the system.
A second serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to DVFS.
Both control interfaces are compliant with the HS-I
2
C specification.
These interfaces support the standard slave mode (100 Kbps), fast mode (400 Kbps), and high-speed mode (3.4
Mbps). The general-purpose I
2
C module using one slave hard-coded address (ID1 = 2Dh). The voltage scaling
dedicated I
2
C module uses one slave hard-coded address (ID0 = 12h). The master mode is not supported.
Addressing:
The device supports seven-bit mode addressing.
It does not support the following features:
• 10-bit addressing
• General call
8.10.1 Access Protocols
or compatibility , the I2C interfaces in the TPS65911x device use the same read/write protocol as other TI power
ICs, based on an internal register size of 8 bits. Supported transactions are described below.
8.10.1.1 Single Byte Access
A write access is initiated by a first byte including the address of the device (7 MSBs) and a write command
(LSB), a second byte provides the address (8 bits) of the internal register, and the third byte represents the data
to be written in the internal register, see Figure 18.
A read access is initiated by:
• A first byte, including the address of the device (7 MSBs) and a write command (LSB)
• A second byte, providing the address (8 bits) of the internal register
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