Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose 23.6 mA BGA 98 MicroStar Junior

TPS659110, TPS659112, TPS659113, TPS659116

SWCS049L –JUNE 2010–REVISED MARCH 2014

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8.3.3.2 PWRHOLD

The PWRHOLD pin can be used as a PWRHOLD signal input or as a general purpose input (GPI). The mode is

selected by the AUTODEV_ON bit, which is part of the boot configuration. When AUTODEV_MODE = 0, the

PWRHOLD feature is selected.

Configured as PWRHOLD, when none of the device POWER ON disable conditions are met, a high level of this

signal causes an OFF-to-ACTIVE state transition of the device and a low level causes a transition back to the

OFF state.

This input signal is level-sensitive and no debouncing is applied. The rising and/or falling edge of PWRHOLD is

highlighted through an associated interrupt if interrupt is unmasked.

When AUTODEV_ON = 1, the pin is used as a GPI. As a GPI, this input can generate a maskable interrupt from

a rising or falling edge of the input. When AUTODEV_ON = 1, a rising edge of NRESPWRON also automatically

sets the DEV_ON bit to 1 to maintain supplies after the switch-on sequence, thus removing the need for the

processor to set the PWRHOLD signal or the DEV_ON bit.

8.3.3.3 BOOT1

This signal determines with which processor the device is working and, hence, which power-up sequence is

needed. For more details, see Switch-ON/-OFF Sequences And Timing. There is no debouncing on this input

signal.

8.3.3.4 NRESPWRON, NRESPWRON2

The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. It is held low until

the ACTIVE state is reached. See Switch-ON/-OFF Sequences And Timing to get detailed timing.

The NRESPWRON2 signal is a second reset output. It follows the state of NRESPWRON but has an open-drain

output with external pullup. The supply for the external pullup must not be activated before the TPS65911 device

is in control of the output state (that is, not earlier than during first power-up sequence slot). In off mode, the

NRESPWRON2 output has weak internal pulldown.

8.3.3.5 CLK32KOUT

This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,

depending on the boot mode. It can be enabled and disabled by register bit, during the ACTIVE state of the

device. The CLK32KOUT output can also be enabled or not during the SLEEP state of the device depending on

the programming of the SLEEPMASK register.

8.3.3.6 PWRON

The PWRON input is connected to an external button. If the device is in the OFF or SLEEP state, a debounced

falling edge (PWRON input low for minimum of 100 ms) causes an OFF-to-ACTIVE state or a SLEEP-to-ACTIVE

state transition of the device. If the device is in active mode, then a low level on this signal generates an

interrupt. If the PWRON signal is low for more than the PWON_TO_OFF_DELAY delay and the corresponding

interrupt is not acknowledged by the processor within 1 second, the device goes into the OFF state. See Figure 5

and Figure 6 for PWRON behaviour.

8.3.3.7 INT1

The INT1 signal (default active low) warns the host processor of any event that has occurred on the TPS65911

device. The host processor can then poll the interrupt from the interrupt status register through I

C to identify the

interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG

enable condition during a fixed delay, t

DOINT1

(only), when the device is in the OFF state (when NRESPWRON is

low).

Any of the interrupt sources can be masked programming the INT_MSK_REG register. When an interrupt is

masked its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt source

masking can be used to mask a device switch-on event. Because interrupt flag active is a POWER ON enable

condition, during t

DOINT1

delay, any interrupt not masked must be cleared to allow immediate turn off of the

device.

Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659116