Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Table 12. Boot Configuration: General Control Bits (continued)
TPS65911x
Register Bit Description
Fixed Boot EEPROM Boot
0: GPIO5 falling-edge detection interrupt
not masked
INT_MSK3_REG GPIO5_F_IT_MSK 1 x
1: GPIO5 falling-edge detection interrupt
masked
0: GPIO5 rising-edge detection interrupt
not masked
INT_MSK3_REG GPIO5_R_IT_MSK 0 x
1: GPIO5 rising-edge detection interrupt
masked
0: GPIO4 falling-edge detection interrupt
not masked
INT_MSK3_REG GPIO4_F_IT_MSK 1 x
1: GPIO4 falling-edge detection interrupt
masked
0: GPIO4 rising-edge detection interrupt
not masked
INT_MSK3_REG GPIO4_R_IT_MSK 0 x
1: GPIO4 rising-edge detection interrupt
masked
0: GPIO0 confiured as push-pull output
GPIO0_REG GPIO_ODEN Push-pull x
1: GPIO0 configured as open-drain output
0: Watchdog disabled
WATCHDOG_REG WATCHDOG_EN 1 x
1: Watchdog enabled, periodic operation
with 100 s
0: Enable input buffer for external resistive
divider
EEPROM VMBBUF_BYPASS Disable buffer x
1: In single-cell system, disable buffer for
low power
Select threshold for boot gating
VMBCH_REG VMBCH_SEL[5:1] 3.1 V x
comparator COMP1, 2.5–3.5 V.
0: PWRHOLD pin is used as PWRHOLD
feature.
1, PWRHOLD pin
EEPROM AUTODEV_ON x
1: PWRHOLD pin is GPI. After power on,
is GPI
DEV_ON set high internally, no processor
action needed to maintain supplies.
0: PWRDN signal will be active-low.
EEPROM PWRDN_POL Active-low x
1: PWRDN signal will be active-high.
8.3.3 Control Signals
8.3.3.1 SLEEP
When none of the device SLEEP-disable conditions are met, a falling edge (default, or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default, or falling edge, depending on the programmed polarity) causes a transition back to the ACTIVE state.
This input signal is level-sensitive and no debouncing is applied.
While the device is in the SLEEP state, predefined resources are automatically set in their low-power mode or
off. Resources can be kept in their active mode (full-load capability) by programming the
SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power
resource. If the bit is set to 1, then that resource stays in active mode when the device is in the SLEEP state.
32KCLKOUT is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained
in the SLEEP state if the corresponding mask bit is set.
The status (low or high) of GPO0, GPO6, GPO7, and GPO8 are also controlled by the SLEEP signal, to allow
enabling and disabling of external resources during sleep.
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