Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Table 11. Boot Configuration: Power Sequence Control Bits (continued)
TPS65911x
Register Bit Description
Fixed Boot EEPROM Boot
LDO4_REG SEL[7:2] LDO4 voltage selection 1.2 V x
EEPROM LDO4 time slot 2 x
LDO5_REG SEL[6:2] LDO5 voltage selection LDO5 voltage: 1 V x
EEPROM LDO5 time slot Off x
LDO6_REG SEL[6:2] LDO6 voltage selection LDO6 voltage: 1 V x
EEPROM LDO6 time slot Off x
LDO7_REG SEL[6:2] LDO7 voltage selection 1.2 V x
EEPROM LDO7 time slot 5 x
LDO8_REG SEL[6:2] LDO8 voltage selection 1.0 V x
EEPROM LDO8 time slot 7 x
CLK32KOUT pin CLK32KOUT time slot 5 x
NRESPWRON,
NRESPWRON time slot 10 x
NRESPWRON2 pin
GPIO0 pin GPIO0 time slot 1 x
GPIO2 pin GPIO2 time slot Off x
GPIO6 pin GPIO6 time slot 6 x
GPIO7 pin GPIO7 time slot 5 x
Table 12. Boot Configuration: General Control Bits
TPS65911x
Register Bit Description
Fixed Boot EEPROM Boot
0: VRTC LDO will be in low-power mode
during OFF state.
VRTC_REG VRTC_OFFMASK 0 x
1: VRTC LDO will be in full-power mode
during OFF state.
0: Clock source is crystal/external clock.
DEVCTRL_REG CK32K_CTRL Crystal x
1: Clock source is internal RC oscillator.
0: No impact
DEVCTRL_REG DEV_ON 0 x
1: Will maintain device on, in ACTIVE or
SLEEP state
Boot sequence time slot duration:
DEVCTRL2_REG TSLOTD 0: 0.5 ms 2 ms x
1: 2 ms
0: Turn off device after PWRON long-
press not allowed.
DEVCTRL2_REG PWON_LP_OFF 1 x
1: Turn off device after PWRON long-
press.
0: No impact
DEVCTRL2_REG PWON_LP_RST 1 x
1: Reset digital core when device is off
0: INT1 signal will be active-low.
DEVCTRL2_REG IT_POL 0 x
1: INT1 signal will be active-high.
0: Device will automatically switch-on at
NO SUPPLY-to-OFF or BACKUP-to-OFF
transition (device will switch-on when
INT_MSK_REG VMBHI_IT_MSK 1 x
supply is inserted)
1: Start-up reason required before switch-
on (VMBHI event interrupt masked)
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