Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Embedded Power Controller (continued)
Power off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ control bit to
1, power off will follow the power-up sequence in reverse order (the first resource to be powered on will be last to
power off).
The values of VDD1, VDD2, and VDDCtrl set in the boot sequence can be selected from 16 steps. For the whole
range, 100-mV steps are available: 0.6/0.7...1.4/1.5 V. From 0.8 to 1.4 V, additional values with 50-mV step
resolution can be set: 0.85/1.05...1.35 V.
For LDO1, LDO2, and LDO4 all levels from 1.0 to 3.3 V are selectable in the boot sequence with 50-mV steps.
For other LDOs, the level is selectable with 100-mV steps, from 1.0 to 3.3 V.
The device supports three boot configurations, which define the power sequence and several device control bits.
The boot configuration is selectable by the device BOOT1 pin.
BOOT1 Boot Configuration
Floating Test boot mode
0 Fixed boot mode
1 EEPROM boot mode
The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.
Table 11 and Table 12 describe the power sequence and general control bits defined in the boot sequence,
respectively.
Fixed boot mode is the same in all part numbers while EEPROM boot mode is different in each part number. For
EEPROM boot mode description refer to the User Guide for the selected part number.
Table 11. Boot Configuration: Power Sequence Control Bits
TPS65911x
Register Bit Description
Fixed Boot EEPROM Boot
VDD1 voltage level selection for boot.
VDD1_OP_REG/VDD1_SR_R
Levels available:
1.2 V x
EG
0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V
VDD1_REG VGAIN_SEL VDD1 gain selection, x1 or x2 x1 x
EEPROM VDD1 time slot selection 3 x
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Enable skip x
VDD2 voltage level selection for boot.
VDD2_OP_REG/VDD2_SR_R
Levels available:
1.5 V x
EG
0.6/0.7/0.8/0.85/0.9/0.95/.../1.35/1.4/1.5 V
VDD2_REG VGAIN_SEL VDD2 gain selection, x1 or x3 x1 x
EEPROM VDD2 time slot selection 6 x
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Enable skip x
VIO_REG SEL[3:2] VIO voltage selection 1.8 V x
EEPROM VIO time slot selection 4 x
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Enable skip x
VDDCtrl voltage level selection for boot.
VDDCtrl_OP_REG/VDDCtrl_S
Levels available:
Off x
R_REG
0.6/0.7/0.8/0.85/0.9/0.95/../1.35/1.4 V
EEPROM VDDCtrl time slot selection Off x
LDO1_REG SEL[7:2] LDO1 voltage selection 1.05 V x
EEPROM LDO1 time slot Off x
LDO2_REG SEL[7:2] LDO2 voltage selection 1.2 V x
EEPROM LDO2 time slot 7 x
LDO3_REG SEL[6:2] LDO3 voltage selection LDO3 voltage: 1 V x
EEPROM LDO3 time slot Off x
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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659116