Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Embedded Power Controller (continued)
(t
DOINT1
pulse duration defined in Power Control Timing). Interrupt sources expected (if enabled), when the
device is off:
– RTC alarm interrupt
– First-time input voltage rising above the VMBHI threshold (depending on the boot mode used) and input
voltage > VMBCH threshold. The interrupt corresponding to this last condtion is VMBCH_IT in the
INT_STS_REG register.
– Or HDRST reset release generates a POWER ON enable condition during a fixed delay t
DOINT1
Interrupt flag active generates a POWER ON enable condition pulse of length t
DOINT1
only when the device is in
the OFF state (when the NRESPWRON signal is low). The POWER ON enable condition pulse occurs only if the
interrupt status bit is initially low (no previous interrupt pending in the status register). The interrupt status register
must first be cleared to allow device power off during the t
DOINT1
pulse duration.
GPIO2 cannot be used to turn on the device, even if its associated interrupt is not masked. The GPIO0, GPIO1,
GPIO3, GPIO4, or GPIO5 signals can be used to turn on the device, if its associated interrupt is not masked.
Note: The watchdog interrupt is not a power on event, but will wake up the device from sleep mode.
Device POWER ON disable conditions:
• PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled though
register programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG
register.
• Or die temperature has reached the thermal shutdown threshold (THERM_TS = 1).
• Or DEV_OFF or DEV_OFF_RST control bit is set to 1 (DEV_OFF value is cleared when the device is in OFF
state).
Note: If the DEV_ON bit is set to 1, after switch-off, the device will switch back on. To keep the device off,
DEV_ON must be cleared first.
Device SLEEP enable conditions:
• SLEEP signal low level (default, or high level depending on the programmed polarity)
• And DEV_SLP control bit is set to 1.
• And interrupt flag inactive (default INT1 high): no nonmasked interrupt is pending.
The SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal in the active
polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 once, after device
turn-on.
Device reset scenarios:
The device has three reset scenarios:
• Full reset: All digital logic of device is reset.
– Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR
• General reset: No impact on the RTC, backup registers, or interrupt status.
– Caused by PWON_LP_RST bit set high
– Or DEV_OFF_RST bit set high
– Or HDRST input set high
• Turnoff: Power reinitialization in off/backup mode.
A mapping of digital registers to these reset scenarios is described in Table 15.
8.3.2 BOOT Configuration And Switch-ON/-OFF Sequences
The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE transition
occurs. The power-on sequence has 15 sequencial time slots to which resources (DCDCs, LDOs, 32-kHz clock,
GPIO0, GPIO2, GPIO6, GPIO7) can be assigned. The time slot length can be selected to be 0.5 ms or 2 ms. If a
resource is not assigned to any time slot, it will be in off mode after the power-on sequence and the voltage level
can be changed through the register SEL bits before enabling the resource.
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