Datasheet

1.2 V
EN1
PFM (pulse
skipping) mode
SW1
VDD1/VFB1
0.8 V
PFM (pulse
skipping) mode
PFM (pulse skipping) mode
PWM mode PWM mode
t
dDVSEN
t
dDVSENL
t
dDVSEN
TSTEP[2:0]=001
TSTEP[2:0]=011
t
dDVSENL
SWCS049-011
TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
7.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
NOTE: Register setting: VDD1_EN1=1, SEL[6:0]=hex13 in VDD1_SR_REG
Figure 11. VDD1 Supply Voltage Control Through EN1
Table 9. VDD1 Supply Voltage Control Through EN1 Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dDVSEN
: EN1 (or EN2) edge to VDD1 (or VDD2)
2 × t
CK32k
= 62 µs
voltage change delay
TSTEP[2:0] = 001 32
TSTEP[2:0] = 011
t
dDVSENL
: VDD1 (or VDD2) voltage settling delay 0.4/7.5 = 53 µs
(default)
TSTEP[2:0] = 111 160
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