Datasheet
TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014
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Device SLEEP State Control (continued)
Table 6. Device SLEEP State Control Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SLEEP falling-edge to
supply n low-power mode
t
ACT2SLP
2 × t
CK32k
= 62 3 × t
CK32k
= 94 µs
(SLEEP resynchronization
delay)
SLEEP falling-edge to
t
ACT2SLPCK32K
156 t
ACT2SLP
+ 3 × t
CK32k
188 µs
CLK32KOUT low
SLEEP rising edge to
t
SLP2ACT
supply in high-power 8 × t
CK32k
= 250 9 × t
CK32k
= 281 µs
mode
SLEEP rising edge to
t
SLP2ACTCK32K
344 t
SLP2ACT
+ 3 × t
CK32k
375 µs
CLK32KOUT running
SLEEP rising edge to time
step 1 of the turn-on
t
dSLPON1
281 t
SLP2ACT
+ 1 × t
CK32k
312 µs
sequence from SLEEP
state
turn-on sequence step
duration, from SLEEP
state
TSLOT_LENGTH[1:0] =
0
00
t
dSLPONST
TSLOT_LENGTH[1:0] = µs
200
01
TSLOT_LENGTH[1:0] =
500
10
TSLOT_LENGTH[1:0] =
2000
11
VDD1, VDD2, or VIO turn-
t
dSLPONDCDC
on delay from turn-on 2 × t
CK32k
= 62 µs
sequence time step
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