Datasheet

SWCS049-007
SLEEP
t
ACT2SLP
VIO/VFBIO
1.8 V
PWM mode
LDO5
VDD2/VFB2
VDD1/VFB1
LDO4
LDO3
LDO8
LDO6
CLK32KOUT
SWIO
SW2
SW1
1.8 V
Low Power mode
1.8 V
PWM mode
1.8 V
ACTIVE mode
1.8 V
Low-power mode
1.8 V
ACTIVE mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
3.3 V
Pulse skip mode
1.2 V
PWM mode
Of
f
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
3.3 V
ACTIVE mode
3.3V
Low-power mode
Off
Off
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
3.3 V
ACTIVE mode
1.2 V
PWM mode
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
t
SLP2ACT
t
ACT2SLPCK32K
t
SLP2ACTCK32K
t
dSLPON1
t
dONDCDCSLP
t
dSLPONST
t
dSLPONST
TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Device State Control Through PWRON Signal (continued)
Table 5. Power Control Timing Characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dONPWHOLD
: delay to set high PWRHOLD signal or
DEV_ON control bit after NRESPWON released to t
dOINT1
– t
DSONT
= 970
(1)
ms
keep on the supplies
PWRON falling-edge to
t
dPWRONLP
: PWRON long-press delay 4 s
PWRON_LP_IT
PWRON_LP_IT to
t
dPWRONLPTO
: PWROW long-press interrupt
NRESPWRON falling- 1 s
(PWRON_LP_IT) to supplies switch-off
edge
(1) T
dSONT
= 30 ms, as in example boot sequence.
7.2 Device SLEEP State Control
NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, LDO3_SETOFF = 1,
LDO4_SETOFF = 1, LDO8_KEEPON = 1.
Figure 7. Device SLEEP State Control
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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659116