Datasheet

SWCS049-004
PWRHOLD
VIO
LDO5
VDD2
VDD1
LDO4
LDO3
LDO8
LDO6
CLK32KOUT
NRESPWRON
t
pd2
t
dsON1
t
dsON2
t
dsON3
t
dsON4
t
dsON5
t
dsON6
t
dsON16
t
pd1
Switch-off sequence
t : Switch-on sequence
ond
NRESPWRON2
t
dsON15
i
TPS659110, TPS659112, TPS659113, TPS659116
www.ti.com SWCS049L –JUNE 2010–REVISED MARCH 2014
Switch-ON/-OFF Sequences And Timing (continued)
Note:: Figure 4 is for illustrative purposes only and does not describe any actual TPS65911x part number.
Figure 4. Boot Sequence Example with 2-ms Time Slot and Simultaneous Switch-Off of Resources
Table 4. Timing Characteristics for Boot Sequence Example
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dsON1
PWRHOLD rising edge to VIO, LDO5 enable delay 66 × t
CK32k
= 2060 µs
t
dsON2
VIO to VDD2 enable delay 64 × t
CK32k
= 2000 µs
t
dsON3
VDD2 to VDD1 enable delay 64 × t
CK32k
= 2000 µs
t
dsON4
VDD1 to LDO4 enable delay 64 × t
CK32k
= 2000 µs
t
dsON5
LDO4 to LDO3, LDO8 enable delay 64 × t
CK32k
= 2000 µs
t
dsON6
LDO3 to LDO6 enable delay 64 × t
CK32k
= 2000 µs
9 × 64 × t
CK32k
=
t
dsON7
LDO6 to CLK32KOUT rising-edge delay µs
18000
CLK32KOUT to NRESPWON, NRESPWON2 rising-
t
dsON16
64 × t
CK32k
= 2000 µs
edge delay
t
dsONT
Total switch-on delay 32 ms
PWRHOLD falling-edge to NRESPWON,
t
pd1
2 × t
CK32k
= 62.5 µs
NRESPWON2 falling-edge delay
t
pd1b
NRESPWON falling-edge to CLK32KOUT low delay 3 × t
CK32k
= 92 µs
PWRHOLD falling-edge to supplies and reference
t
pd2
5 × t
CK32k
= 154 µs
disable delay
7 Power Control Timing
7.1 Device State Control Through PWRON Signal
Figure 5 shows the device state control through PWRON signal.
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