Datasheet
SWCS049-001
VFB2
PWRON
VREF
Test interface
CLK32KOUT
3
OSC32KIN
OSC32KOUT
TESTV
SLEEP
NRESPWRON
PWRDN
BOOT1
(LDO)
SDA_SDI
VRTC
and POR
(LDO)
BACKUP
Mgmt
3
(SMPS)
5V
VCC6
VCC3
VCC5
VCC7
VDDIO
AGNDAGND
REFGND
OSC
32-kHz
SCL_SCK
I C
2
C
BB
LDO1
320 mA
LDO2
LDO7
LDO8
LDO3
200 mA
LDO3
LDO4
3
(SMPS)
LDO5
VCC4
VCCS
Watchdog
Analog
references
TRIP
DRVH
DRVL
SW
VOUT
V5IN
GNDC
VBST
NRESPWRON2
HDRST
REFGND
VFB
PWRHOLD
LDO2
320 mA
LDO4
50 mA
LDO5
300 mA
LDO8
300 mA
LDO7
300 mA
LDO6
LDO6
300 mA
VBACKUP
EN1
EN2
I C
2
VDD1
VDD2
VIO
R
trip
C
C
1
boost
C
V5IN
C
C
o
VIN
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
INT1
1 to 3.3 V,
50-mV step
1 to 3.3 V,
100-mV step
1 to 3.3 V,
100-mV step
COMP
1
COMP
2
VCC1
SW1
GND1
VFB1
VCC2
SW2
GND2
3
VRTC
VCCIO
SWIO
GNDIO
VFBIO
LDO1
VDDIO
1 to 3.3 V,
50-mV step
1 to 3.3 V,
50-mV step
1 to 3.3 V,
100-mV step
1 to 3.3 V,
100-mV step
1 to 3.3 V,
100-mV step
Real
time
clock
Bus
control
Power
control
state
machine
0.6 to 1.5 V,
12.5-mV step
0.6 to 1.5 V,
12.5-mV step,
1.5 A
0.6 to 1.4 V,
12.5-mV step
Controller
1.5 A @ 0.6 to 1.5 V*
1.5 A @ 0.6 to 2.2 V*
1.3 A @ 1.5 V
1.2 A @ 1.8 V
1.1 A @ 2.2 and 3.3 V
TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014
www.ti.com
*: For details on supported levels, see VDD1 SMPS, VDD2 SMPS, and Table 10.
Figure 1. Top-Level Diagram
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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659116