Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Table 95. PWM_CTRL1_REG (continued)
Type RW
7 6 5 4 3 2 1 0
Reserved PWM_FREQ
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RO 0x00
R returns
0s
1:0 PWM_FREQ Frequency of PWM: RW 0x0
00: 500 Hz
01: 250 Hz
10: 125 Hz
11: 62.5 Hz
Table 96. PWM_CTRL2_REG
Address Offset 0x6F
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description PWM duty cycle.
Type RW
7 6 5 4 3 2 1 0
FREQ_DUTY_CYCLE
Bits Field Name Description Type Reset
7:0 FREQ_DUTY_CYCLE Duty cycle of PWM: RW 0x00
00000000: 0/256
...
11111111: 255/256
Table 97. SPARE_REG
Address Offset 0x70
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Spare functional register
Type RW
7 6 5 4 3 2 1 0
SPARE
Bits Field Name Description Type Reset
7:0 SPARE Spare bits RW 0x00
Table 98. VERNUM_REG
Address Offset 0x80
Physical Address Instance (RESET DOMAIN: FULL RESET)
Description Silicon version number
Type RW
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