Datasheet

TPS659110, TPS659112, TPS659113, TPS659116
SWCS049L –JUNE 2010–REVISED MARCH 2014 www.ti.com
Bits Field Name Description Type Reset
7 PWRDN_IT_MSK PWRDN interrupt mask RW 1
6 VMBCH2_L_IT_MSK Comparator2 input below threshold detection interrupt mask RW 1
5 VMBCH2_H_IT_MSK Comparator2 input above threshold detection interrupt mask RW 1
4 WTCHDG_IT_MSK Watchdog interrupt mask. RW 1
3 GPIO5_F_IT_MSK GPIO5 falling-edge detection interrupt mask. RW 1
2 GPIO5_R_IT_MSK GPIO5 rising-edge detection interrupt mask. RW 1
1 GPIO4_F_IT_MSK GPIO4 falling-edge detection interrupt mask. RW 1
0 GPIO4_R_IT_MSK GPIO4 rising-edge detection interrupt mask. RW 1
Table 81. GPIO0_REG
Address Offset 0x60
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description GPIO0 configuration register
Type RW
7 6 5 4 3 2 1 0
GPIO_SLEEP Reserved GPIO_ODEN GPIO_DEB GPIO_PDEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7 GPIO_SLEEP
(1)
1: as GPO, force low RW 0
0: No impact, keep as in active mode
6 Reserved Reserved bit RO 0
R returns
0s
5 GPIO_ODEN Selection of output mode, EEPROM bit RW 0
0: Push-pull output
1: Open-drain output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit will be set to 1 by a
TURNOFF reset
4 GPIO_DEB GPIO input debouncing time configuration: RW 0
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate
3 GPIO_PDEN GPIO pad pulldown control: RW 0
1: Pulldown is enabled
0: Pulldown is disabled
2 GPIO_CFG Configuration of the GPIO pad direction: RW 0
When 0, the pad is configured as an input
When 1, the pad is configured as an output
(Default value: See boot configuration)
1 GPIO_STS Status of the GPIO pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0
GPIO assigned to power-up sequence, this bit will be in TURNOFF reset
(1) The GPIO_SLEEP bit is a bit available only for GPIO_0/2/6/7.This bit will be take into account and be effective only if the GPIO_0/2/6/7
is associated to a TIME_SLOT. It means that this bit is useful only if the GPIO is part of the POWER UP SEQUENCE. Please note that
in this case the associated GPIO will be set as GPO. GPIO_SLEEP bit is a bit related to the PMU sleep mode only, No action in
ACTIVE mode. It is used to define SLEEP mode state for GPIO 0/2/6/7.
Table 82. GPIO1_REG
Address Offset 0x61
Physical Address Instance (RESET DOMAIN: GENERAL
RESET)
Description GPIO1 configuration register
Type RW
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