Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Table 6-66. INT_MSK2_REG
Address Offset 0x53
Physical Address Instance
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type RW
7 6 5 4 3 2 1 0
GPIO0_F_IT_M GPIO0_R_IT_
Reserved
SK MSK
Bits Field Name Description Type Reset
7:2 Reserved Reserved bit RW 0
1 GPIO0_F_IT_MSK GPIO_CKSYNC falling edge detection interrupt mask. RW 0
0 GPIO0_R_IT_MSK GPIO_CKSYNC rising edge detection interrupt mask. RW 0
Table 6-67. GPIO0_REG
Address Offset 0x60
Physical Address Instance
Description GPIO0 configuration register
Type RW
7 6 5 4 3 2 1 0
Reserved GPIO_DEB GPIO_PUEN GPIO_CFG GPIO_STS GPIO_SET
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO 0x0
R returns
0s
4 GPIO_DEB GPIO_CKSYNC input debouncing time configuration: RW 0
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate
3 GPIO_PUEN GPIO_CKSYNC pad pull-up control: RW 1
1: Pull-up is enabled
0: Pull-up is disabled
2 GPIO_CFG Configuration of the GPIO_CKSYNC pad direction: RW 0
When 0, the pad is configured as an input
When 1, the pad is configured as an output
1 GPIO_STS Status of the GPIO_CKSYNC pad RO 1
0 GPIO_SET Value set on the GPIO output when configured in output mode RW 0
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 93
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109