Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Table 6-61. RESERVED
Address Offset 0x49
Physical Address Instance
Description Reserved register
Type RW
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED Reserved bit RW 0
Table 6-62. RESERVED
Address Offset 0x4A
Physical Address Instance
Description Reserved register
Type RW
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED Reserved bit RW 0x00
Table 6-63. INT_STS_REG
Address Offset 0x50
Physical Address Instance
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
RTC_PERIOD_ RTC_ALARM_I
HOTDIE_IT PWRHOLD_IT PWRON_LP_IT PWRON_IT VMBHI_IT VMBDCH_IT
IT T
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT RTC period event interrupt status. RW 0
W1 to Clr
6 RTC_ALARM_IT RTC alarm event interrupt status. RW 0
W1 to Clr
5 HOTDIE_IT Hot die event interrupt status. RW 0
W1 to Clr
4 PWRHOLD_IT PWRHOLD event interrupt status. RW 0
W1 to Clr
3 PWRON_LP_IT PWRON Long Press event interrupt status. RW 0
W1 to Clr
2 PWRON_IT PWRON event interrupt status. RW 0
W1 to Clr
1 VMBHI_IT VBAT > VMBHI event interrupt status RW 0
W1 to Clr
0 VMBDCH_IT VBAT > VMBDCH event interrupt status. RW 0
Active only if Main Battery comparator VMBCH programmable threshold W1 to Clr
is not bypassed (VMBCH_SEL[1:0] ≠ 00)
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 91
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109