Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
Table 6-54. SLEEP_KEEP_RES_ON_REG
Address Offset 0x42
Physical Address Instance
Description Configuration Register keeping, during the SLEEP state of the device (but then supply state can be
overwritten programming ST[1:0]):
- The full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DCDC converter
- 32KHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die Thermal monitoring on
Control bit value has no effect if the resource is off.
Type RW
7 6 5 4 3 2 1 0
THERM_KEEP CLKOUT32K_K VRTC_KEEPO I2CHS_KEEPO VDD3_KEEPO VDD2_KEEPO VDD1_KEEPO
VIO_KEEPON
ON EEPON N N N N N
Bits Field Name Description Type Reset
7 THERM_KEEPON When 1, thermal monitoring is maintained during device SLEEP state. RW 0
When 0, thermal monitoring is turned off during device SLEEP state.
6 CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state. RW 0
N When 0, CLK32KOUT output is set low during device SLEEP state.
5 VRTC_KEEPON When 1, LDO regulator full load capability (ACTIVE mode) is maintained RW 0
during device SLEEP state.
When 0, the LDO regulator is set or stays in low power mode during
device SLEEP state.
4 I2CHS_KEEPON When 1, high speed internal clock is maintained during device SLEEP RW 0
state.
When 0, high speed internal clock is turned off during device SLEEP
state.
3 VDD3_KEEPON When 1, VDD3 SMPS high power mode is maintained during device RW 0
SLEEP state. No effect if VDD3 working mode is low power.
When 0, VDD3 SMPS low power mode is set during device SLEEP
state.
2 VDD2_KEEPON If VDD2_EN1&2 control bit = 0 (default setting): RW 0
When 1, VDD2 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD2 working mode is PFM.
When 0, VDD2 SMPS PFM mode is set during device SLEEP state.
1 VDD1_KEEPON If VDD1_EN1&2 control bit=0 (default setting): RW 0
When 1, VDD1 SMPS PWM mode is maintained during device SLEEP
state. No effect if VDD1 working mode is PFM.
When 0, VDD1 SMPS PFM mode is set during device SLEEP state.
0 VIO_KEEPON If VIO_EN1&2 control bit=0 (default setting): When 1, VIO SMPS PWM RW 0
mode is maintained during device SLEEP state. No effect if VIO working
mode is PFM.
When 0, VIO SMPS PFM mode is set during device SLEEP state.
84 Detailed Description Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109