Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
Table 6-52. DEVCTRL2_REG
Address Offset 0x40
Physical Address Instance
Description Device control register
Type RW
7 6 5 4 3 2 1 0
SLEEPSIG_PO PWRON_LP_O PWRON_LP_R
Reserved TSLOT_LENGTH IT_POL
L FF ST
Bits Field Name Description Type Reset
7:6 Reserved Reserved bit RO 0x0
R returns
0s
5:4 TSLOT_LENGTH Time slot duration programming (EEPROM bit): RW 0x3
When 00 : 0 µs
When 01 : 200 µs
When 10 : 500 µs
When 11 : 2 ms
3 SLEEPSIG_POL When 1, SLEEP signal active high RW 0
When 0, SLEEP signal active low
2 PWRON_LP_OFF When 1, allows device turn-off after a PWRON long press (signal low). RW 1
1 PWRON_LP_RST When 1, allows digital core reset when the device is OFF after a RW 0
PWRON long press (signal low).
0 IT_POL INT1 interrupt pad polarity control signal (EEPROM bit): RW 0
When 0, active low
When 1, active high
82 Detailed Description Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109