Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Table 6-51. DEVCTRL_REG
Address Offset 0x3F
Physical Address Instance
Description Device control register
Type RW
7 6 5 4 3 2 1 0
SR_CTL_I2C_ DEV_OFF_RS
Reserved RTC_PWDN CK32K_CTRL DEV_ON DEV_SLP DEV_OFF
SEL T
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO 0
R returns
0s
6 RTC_PWDN When 1, disable the RTC digital domain (clock gating and reset of RTC RW 1
registers and logic).
This register bit is not reset in BACKUP state (EEPROM bit)
5 CK32K_CTRL Internal 32-kHz clock source control bit (EEPROM bit): RW 1
when 0, the internal 32-kHz clock source is the crystal oscillator or an
external 32-kHz clock in case the crystal oscillator is used in bypass
mode
when 1, the internal 32-kHz clock source is the RC oscillator.
4 SR_CTL_I2C_SEL Smartreflex registers access control bit: RW 0
when 0: access to smartreflex registers by smartreflex I2C
when 1: access to smartreflex registers by control I2C The smartreflex
registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG and
VDD2_SR_REG.
3 DEV_OFF_RST Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state RW 0
transition (switch-off event) and activate reset of the digital core.
2 DEV_ON Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if RW 0
DEV_OFF = 0 and DEV_OFF_RST = 0).
1 DEV_SLP Write 1 allows SLEEP device state (if DEV_OFF = 0 and RW 0
DEV_OFF_RST = 0).
Write ‘0’ will start an SLEEP to ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
0 DEV_OFF Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state RW 0
transition (switch-off event). This bit is cleared in OFF state.
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 81
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