Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Table 6-43. VAUX2_REG
Address Offset 0x33
Physical Address Instance
Description VAUX2 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Supply voltage (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.8 V
SEL[1:0] = 10 : 2.9 V
SEL[1:0] = 11 : 3.3 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 6-44. VAUX33_REG
Address Offset 0x34
Physical Address Instance
Description VAUX33 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Supply voltage (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.0 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 3.3 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 77
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