Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Table 6-39. VDD3_REG
Address Offset 0x27
Physical Address Instance
Description VDD2 voltage selection register for smartreflex.
This register can be accessed by both control and smartreflex I
2
C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved CKINEN ST
Bits Field Name Description Type Reset
7:3 Reserved Reserved bit RO 0x00
R returns
0s
2 CKINEN Enable 1MHz clock synchronization RW 1
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
Table 6-40. VDIG1_REG
Address Offset 0x30
Physical Address Instance
Description VDIG1 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Supply voltage (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.2 V
SEL[1:0] = 01 : 1.5 V
SEL[1:0] = 10 : 1.8 V
SEL[1:0] = 11 : 2.7 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 75
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109