Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
When a supply is controlled through SCLSR_EN1 or SCLSR_EN2 signals, its state is no longer driven by
the device SLEEP state.
6.3.3.9 GPIO_CKSYNC
GPIO_CKSYNC is a configurable open-drain digital I/O: directivity, debouncing delay and internal pullup
can be programmed in the GPIO0_REG register. GPIO_CKSYNC cannot be used to turn on the device
(OFF-to-ACTIVE state transition), even if its associated interrupt is not masked, but can be used as an
interrupt source to wake up the device from SLEEP-to-ACTIVE state.
Programming DCDCCKEXT = 1, VDD1, VDD2, VIO, and VDD3 DC-DC switching can be synchronized
using a 3-MHz clock set though the GPIO_CKSYNC pin.
6.3.4 Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
Dynamic voltage frequency scaling (DVFS) operation: a supply voltage value corresponding to a targeted
frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.
The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed
value is limited to 12.5 mV/µs, fixed value. Adaptative voltage scaling (AVS) operation: a supply voltage
value corresponding to a supply voltage adjustment is programmed in VDD1_SR_REG or
VDD2_SR_REG registers. The supply voltage is then intended to be tuned by the digital core supplied,
based its performance self-evaluation. The slew rate of VDD1 or VDD2 voltage supply reaching a new
programmed value is programmable though the VDD1_REG or VDD2_REG register, respectively.
A serial control interface (SR-I
2
C) is dedicated to SmartReflex applications such as DVFS and class 3
AVS, and thus gives access to the VDD1_OP_REG, VDD1_SR_REG, and VDD2_OP_REG,
VDD2_SR_REG register.
A general-purpose serial control interface (CTL-I
2
C) also gives access to these registers, if
SR_CTL_I2C_SEL control bit is set to 1 in the DEVCTRL_REG register (default inactive).
Both control interfaces are compliant with HS-I
2
C specification (100 kbps, 400 kbps, or 3.4 Mbps).
Figure 6-2 shows an example of a SmartReflex operation. To optimize power efficiency, the voltage
domains of the host processor uses the DVFS and AVS features provided by SmartReflex.
50 Detailed Description Copyright © 2010–2014, Texas Instruments Incorporated
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