Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
6.3.3.6 PWRON
A falling edge on this signal causes after t
dbPWRONF
debouncing delay (defined in Figure 5-4 and Table 5-5)
an OFF-to-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding
interrupt (PWRON_IT) active. The PWRON input is connected to an external push-button. The built-in
debouncing time defines a minimum button press duration that is required for button press detection. Any
button press duration which is lower than this value is ignored, considered an accidental touch.
After an OFF-to-ACTIVE state transition, the PMIC maintains ACTIVE during t
dOINT
delay, if the button is
released. After this delay if none of the device enabling conditions is set by the processor supplied, the
PMIC automatically turns off. If the button is not released, the PMIC maintains ACTIVE up to t
dPWRONLPTO
,
because PWRON low is a device enabling condition. After a SLEEP-to-ACTIVE state transition, the PMIC
maintains ACTIVE as long as an interrupt is pending.
If the device is already in ACTIVE state, a PWRON low level makes the corresponding interrupt
(PWRON_IT) active.
When the PMIC is in ACTIVE mode, if the button is pressed for longer time than t
dPWRONLP
, the PMIC
generates the PWON_LP_IT interrupt. If the processor does not acknowledge the long press interrupt
within a period of t
dPWRONLPTO
– t
dPWRONLP
, the PMIC goes to OFF mode and shuts down the DCDCs and
LDOs.
6.3.3.7 INT1
INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910
device. The host processor can then poll the interrupt from the interrupt status register through I
2
C to
identify the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the
INT_STS_REG register. The polarity of INT1 can be set by programming the IT_POL control bit.
Any (not masked or masked) interrupt detection causes a POWER ON enable condition during a fixed
delay t
DOINT1
(only) when the device is in OFF state (when NRESPWON signal is low). Any (not masked)
interrupt detection is causing a device wakeup from SLEEP state up to acknowledge of the pending
interrupt. Any of the interrupt sources can be masked by programming the INT_MSK_REG register. When
an interrupt is masked, its corresponding interrupt status bit is still updated, but the INT1 flag is not
activated.
Interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a
POWER ON enable condition during t
DOINT1
delay, any interrupt not masked must be cleared to allow turn
off of the device after the t
DOINT1
POWER ON enable pulse duration.. See section: Interrupts, for interrupt
sources definition.
6.3.3.8 SDASR_EN2 and SCLSR_EN1
SDASR_EN2 and SCLSR_EN1 are the data and clock signals of the serial control interface (SR-I
2
C)
dedicated to SmartReflex applications. These signals can also be programmed to be used as enable
signals of one or several supplies, when the device is on (NRESPWRON high). A resource assigned to
SDASR_EN2 or SCLSR_EN1 control automatically disables the serial control interface.
Programming EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or sleep state of any LDO
type supplies.
Programming EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or low-power state (PFM
mode) of SMPS type supplies.
SDASR_EN2 and SCLSR_EN1 can be used to set output voltage of VDD1 and VDD2 SMPS from a roof
to a floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG, and teh VDD1_SR_REG,
VDD2_SR_REG registers. Tun-off of VDD1 and VDD2 can also be programmed either in
VDD1_OP_REG, VDD2_OP_REG or in VDD1_SR_REG, VDD2_SR_REG registers.
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 49
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